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CY62167EV30 MoBL(R)
16-Mbit (1M x 16 / 2M x 8) Static RAM
Features
* * * * TSOP I package configurable as 1M x 16 or as 2M x 8 SRAM Very high speed: 45 ns Wide voltage range: 2.20V-3.60V Ultra low standby power -- Typical standby current: 1.5 A -- Maximum standby current: 12 A * Ultra low active power * * * * -- Typical active current: 2.2 mA @ f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed/power Offered in Pb-free 48-ball BGA and 48-pin TSOP I packages significantly reduces power consumption by 99% when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high-impedance state when: the device is deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from the IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory will appear on IO8 to IO15. See the "Truth Table" on page 10 for a complete description of read and write modes.
Functional Description[1]
The CY62167EV30 is a high performance CMOS static RAM organized as 1M words by 16 bits / 2M words by 8 bits. This device features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER
1M x 16 / 2M x 8 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
CE2 BYTE BHE WE OE BLE
Power Down Circuit
CE1 BHE BLE
A11 A12 A13 A14 A15 A16 A17 A18 A19
CE2 CE1
Note 1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation Document #: 38-05446 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised June 04, 2007
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CY62167EV30 MoBL(R)
Pin Configuration[2, 3, 4]
48-Ball FBGA Top View
1 BLE IO 8 IO 9 VSS VCC IO 14 IO 15 A18 2 OE BHE IO 10 IO11 IO 12 IO 13 A19 A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 IO 1 IO3 IO 4 IO 5 WE A11 6 CE2 IO 0 IO 2 VCC Vss IO 6 IO 7 NC A B C D E F G H
48-Pin TSOP I Top View
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 NC BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss IO15/A20 IO7 IO14 IO6 IO13 IO5 IO12 IO4 Vcc IO11 IO3 IO10 IO2 IO9 IO1 IO8 IO0 OE Vss CE1 A0
Product Portfolio
Power Dissipation Product VCC Range (V) Min CY62167EV30LL 2.20 Typ[5] 3.0 Max 3.60 45 Speed (ns) Typ[5] 2.2 Operating ICC (mA) f = 1 MHz Max 4.0 f = fmax Typ[5] 25 Max 30 Standby ISB2 (A) Typ[5] 1.5 Max 12
Notes 2. NC pins are not connected on the die. 3. The BYTE pin in the 48-TSOPI package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOPI package can also be used as a 2M X 8 SRAM by tying the BYTE signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and IO8 to IO14 pins are not used. 4. Ball H6 for the FBGA package can be used to upgrade to a 32M density. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
Document #: 38-05446 Rev. *C
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CY62167EV30 MoBL(R)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage to Ground Potential .............................. -0.3V to 3.9V (VCC(max) + 0.3V DC Voltage Applied to Outputs in High Z State[6, 7] .............. -0.3V to 3.9V (VCC(max) + 0.3V DC Input Voltage[6, 7] .......... -0.3V to 3.9V (VCC(max) + 0.3V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA
Operating Range
Device Range Ambient Temperature VCC[8]
CY62167EV30LL Industrial -40C to +85C 2.2V to 3.6V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 IIX IOZ ICC Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels For FBGA package For TSOP I package IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1mA 1.8 2.2 -0.3 -0.3 -0.3 -1 -1 25 2.2 1.5 45 ns Min 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 0.7
[9]
Typ[5]
Max
Unit V V V V V V V V V A A mA mA A
+1 +1 30 4.0 12
ISB1
Automatic CE Power Down CE1 > VCC - 0.2V or CE2 < 0.2V Current--CMOS Inputs VIN > VCC - 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 3.60V Automatic CE Power Down CE1 > VCC - 0.2V or CE2 < 0.2V, Current--CMOS Inputs VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V
ISB2[10]
1.5
12
A
Capacitance[11]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 6. VIL(min) = -2.0V for pulse durations less than 20 ns. 7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 8. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 9. Under DC conditions the device meets a VIL of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7V. This is applicable to TSOP I package only. 10. Only chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters.
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CY62167EV30 MoBL(R)
Thermal Resistance[11]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 55 16 TSOP I 60 4.3 Unit C/W C/W
AC Test Loads and Waveforms
VCC OUTPUT R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters R1 R2 RTH VTH 2.2V to 2.7V 16667 15385 8000 1.20 2.7V to 3.6V 1103 1554 645 1.75 Unit V
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR[10] Description VCC for Data Retention Data Retention Current VCC = 1.5V, CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min 1.5 10 Typ[5] Max Unit V A
tCDR[11] tR[12]
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform[13]
VCC
CE1 or BHE.BLE
VCC(min) tCDR
DATA RETENTION MODE VDR > 1.5 V
VCC(min) tR
or CE2
Notes 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 13. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
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CY62167EV30 MoBL(R)
Switching Characteristics
Over the Operating Range[14, 15] Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW Z[16] OE HIGH to High Z
[16, 17]
Description
45 ns Min 45 45 10 45 22 5 18 Max
Unit
ns ns ns ns ns ns ns ns 18 ns ns 45 45 ns ns ns 18 ns ns ns ns ns ns ns ns ns ns 18 ns ns
CE1 LOW and CE2 HIGH to Low
Z[16]
10 0
CE1 HIGH and CE2 LOW to High Z[16, 17] CE1 LOW and CE2 HIGH to Power Up CE1 HIGH and CE2 LOW to Power Down BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z[16] BLE / BHE HIGH to HIGH Z[16, 17]
[18]
10
Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z[16, 17] WE HIGH to Low-Z
[16]
45 35 35 0 0 35 35 25 0 10
Notes 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in "AC Test Loads and Waveforms" on page 4. 15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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CY62167EV30 MoBL(R)
Switching Waveforms
Figure 1 shows address transition controlled read cycle waveforms.[19, 20] Figure 1. Read Cycle No. 1
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 2 shows OE controlled read cycle waveforms.[20, 21] Figure 2. Read Cycle No. 2
ADDRESS tRC CE1 CE2 tACE BHE/BLE tDBE tLZBE OE tDOE DATA VALID tHZOE HIGH IMPEDANCE tHZBE tPD tHZCE
DATA OUT
tLZOE HIGH IMPEDANCE tLZCE
VCC SUPPLY CURRENT
tPU
50%
50%
ICC ISB
Notes 19. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 20. WE is HIGH for read cycle. 21. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
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CY62167EV30 MoBL(R)
Switching Waveforms (continued)
Figure 3 shows WE controlled write cycle waveforms.[18, 22, 23] Figure 3. Write Cycle No. 1
tWC ADDRESS tSCE CE1 CE2 tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA IO NOTE 24 tHZOE VALID DATA
tHD
Notes 22. Data IO is high impedance if OE = VIH. 23. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 24. During this period the IOs are in output state. Do not apply input signals.
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CY62167EV30 MoBL(R)
Switching Waveforms (continued)
Figure 4 shows CE1 or CE2 controlled write cycle waveforms.[18, 22, 23] Figure 4. Write Cycle No. 2
tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA
WE
BHE/BLE
tBW
OE DATA IO NOTE 24 tHZOE
tSD VALID DATA
tHD
Figure 5 shows WE controlled, OE LOW write cycle waveforms.[23] Figure 5. Write Cycle No. 3
tWC ADDRESS tSCE CE1 CE2
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATA IO NOTE 24 VALID DATA
tHD
tHZWE
tLZWE
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CY62167EV30 MoBL(R)
Switching Waveforms (continued)
Figure 6 shows BHE/BLE controlled, OE LOW write cycle waveforms.[23] Figure 6. Write Cycle No. 4
tWC ADDRESS
CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA IO NOTE 24 VALID DATA tHD tBW tHA
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CY62167EV30 MoBL(R)
Truth Table
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE BLE X X H L H L L H L L H L X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (IO0-IO15) Data Out (IO0-IO7); High Z (IO8-IO15) High Z (IO0-IO7); Data Out (IO8-IO15) High Z High Z High Z Data In (IO0-IO15) Data In (IO0-IO7); High Z (IO8-IO15) High Z (IO0-IO7); Data In (IO8-IO15) Mode Deselect/Power-Down Deselect/Power Down Deselect/Power Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 Ordering Code CY62167EV30LL-45BVXI CY62167EV30LL-45ZXI Package Diagram Package Type Operating Range Industrial
51-85150 48-ball Fine Pitch Ball Grid Array (Pb-free) 51-85183 48-pin TSOP I (Pb-free)
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CY62167EV30 MoBL(R)
Package Diagrams
Figure 7. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C 1.00 MAX
SEATING PLANE 0.26 MAX. C
51-85150-*D
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CY62167EV30 MoBL(R)
Package Diagrams (continued)
Figure 8. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183
DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05]
1 N
0.020[0.50] TYP.
0.472[12.00]
0.007[0.17] 0.011[0.27]
0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] SEATING PLANE 0.004[0.10] 0.004[0.10] 0.008[0.21] 0.020[0.50] 0.028[0.70] 0.010[0.25] GAUGE PLANE 0-5
0.002[0.05] 0.006[0.15]
51-85183-*A
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CY62167EV30 MoBL(R)
Document History Page
Document Title: CY62167EV30 MoBL(R) 16-Mbit (1M x 16 / 2M x 8) Static RAM Document Number: 38-05446 REV. ** *A ECN NO. 202600 463674 Issue Date 01/23/04 See ECN Orig. of Change AJU NXR Description of Change New Data Sheet Converted from Advance Information to Preliminary Removed `L' bin and 35 ns speed bin from product offering Modified Data sheet to include x8 configurability. Changed ball E3 in FBGA pinout from DNU to NC Changed the ISB2(Typ) value from 1.3 A to 1.5 A Changed the ICC(Max) value from 40 mA to 25 mA Changed Vcc stabilization time in footnote #9 from 100 s to 200 s Changed the AC Test Load Capacitance value from 50 pF to 30 pF Corrected typo in Data Retention Characteristics (tR) from 100 s to tRC ns Changed tOHA, tLZCE, tLZBE, and tLZWE from 6 ns to 10 ns Changed tLZOE from 3 ns to 5 ns. Changed tHZOE, tHZCE, tHZBE, and tHZWE from 15 ns to 18 ns Changed tSCE, tAW, and tBW from 40 ns to 35 ns Changed tPE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Updated 48 ball FBGA Package Information. Updated the Ordering Information table Minor Change: Moved to external web Converted from preliminary to final Changed ICC max spec from 2.8 mA to 4.0 mA for f=1MHz Changed ICC typ spec from 22 mA to 25 mA for f=fmax Changed ICC max spec from 25 mA to 30 mA for f=fmax Added VIL spec for TSOP I package and footnote# 9 Added footnote# 10 related to ISB2 and ICCDR Changed ISB1 and ISB2 spec from 8.5 A to 12 A Changed ICCDR spec from 8 A to 10 A Added footnote# 15 related to AC timing parameters
*B *C
469169 1130323
See ECN See ECN
NSI VKN
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